Integrated circuits (ICs) or chips employ capacitors for charge storage purposes. An example of an IC that employs capacitors for storing charge is a memory IC, such as a dynamic random access memory (DRAM) chip. The level of the charge ("0" or "1") in the capacitor represents a bit of data.
A DRAM chip includes an array of memory cells interconnected by rows and columns. Typically, the row and column connections are referred to as wordlines and bitlines, respectively. Reading data from or writing data to the memory cells is accomplished by activating the appropriate wordlines and bitlines.
Typically, a DRAM memory cell comprises a transistor connected to a capacitor. The transistor includes two diffusion regions separated by a channel, above which is located a gate. Depending on the direction of current flow between the diffusion region, one is referred to as the drain and the other the source. The terms "drain" and "source" are herein used interchangeably to refer to the diffusion regions. The gate is coupled to a wordline and one of the diffusion regions is coupled to a bitline. The other diffusion region is coupled to the capacitor. Applying an appropriate voltage to the gate switches the transistor on, enabling current to flow through channel between the diffusion regions to form a connection between the capacitor and bitline. Switching off the transistor severs this connection by preventing current flowing through the channel.
The charge stored in the capacitor dissipates over time due to current leakage therefrom. Before the charge dissipates to an indeterminate level (below a threshold), the node has to be refreshed.
Continued demand to shrink devices has facilitated the design of DRAMs having greater density and smaller feature size and cell area. To produce cells that occupy less surface area, smaller components such as capacitors are used. However, the use of smaller capacitors results in decreased storage capacity, which can adversely affect the performance and operability of the memory device. For example, sense amplifiers require an adequate signal level to reliably sense the information in the cells. The ratio of storage capacitance to bitline capacitance is crucial in determining the signal level. If the capacitor becomes too small, this ratio may be too small to provide an adequate signal. Also, smaller storage capacity requires higher refresh frequency.
One type of capacitor that is are commonly employed in DRAMs is a trench capacitor. A trench capacitor is a three-dimensional structure formed in the silicon substrate. Increasing the volume or capacitance of the trench capacitor can be achieved by etching deeper into the substrate. As such, increasing the capacitance of the trench capacitor does not increase the surface area of the cell.
A conventional trench capacitor comprises a trench etched into the substrate. The trench is typically filled with n+ doped poly which serves as an electrode of the capacitor (referred to as the storage node). Optionally, a second electrode of the capacitor, referred to as a "buried plate," is formed by outdiffusing n+ dopants from a dopant source into a region of the substrate surrounding the lower portion of the trench. A n+ doped silicate glass such as Arsenic doped silicate glass (ASG) serves as the dopant source. A node dielectric comprising nitride is provided to separate the two electrodes of the capacitor.
In the upper portion of the trench, a dielectric collar is provided to prevent leakage from the node junction to the buried plate. The node dielectric in the upper portion of the trench where the collar is to be formed is removed prior to its formation. Removal of the nitride prevents vertical leakage along the collar.
However, the removal of the upper portion of the nitride layer creates pinholes at the transition between the bottom part the collar and upper edge of the node dielectric. Pinholes degrade the integrity of the node dielectric, and are a substantial source of charge leakage from the trench. This reduces the retention time of the trench capacitor, adversely impacting performance.
To prevent the formation of pinholes, a two step trench etch process has been proposed. First, the trench is partially etched by a reactive ion etch (RIE) to the depth of the collar. The RIE is selective to the hard etch mask. Typical chemistry employed for the RIE includes, for example, NF.sub.3 /HBr/He/O.sub.2. An oxide layer is deposited and etched to form the collar on the trench sidewalls. The etch, which is a RIE, is selective to silicon using, for example, CHF.sub.3 /He/O.sub.2, CHF.sub.3 /Ar, C.sub.4 F.sub.8 /Ar, or CF.sub.4 chemistry. The remaining portion of the trench is etched after collar formation. The node dielectric is then formed over the collar and lower portion of the trench sidewalls. Such a process eliminates the need to remove the upper portion of the node dielectric, thus avoiding pinholes from forming.
Although such two step trench formation is effective in preventing pinholes, the second RIE step for removing silicon may cause excessive erosion of the collar. Degradation of the collar causes leakage to occur. Furthermore, the collar acts as a hard etch mask for the second RIE trench etch, producing a lower portion of the trench having a diameter which is equal to that of the inner circumference of the collar. Thus, the lower portion of the trench is smaller than the upper portion, which has a diameter equal to about the outer circumference of the collar. This is undesirable as it reduces the capacitance of the capacitor.
From the above description, it is desirable to provide a trench capacitor with reduced charge leakage and increased capacitance.